The present invention relates generally to an automated integrated circuit (IC) layout method, and, more particularly, to a place-and-route method that utilizes the same footprint and gridded library cells.
Many ICs, particularly those application-specific integrated circuit (ASIC) and field programmable gate arrays, utilize automation tools to generate layout from small cell blocks. Such automated tools place these pre-built small cell blocks and route interconnects among them according to a designer's specifications.
FIG. 1 is block diagram illustrating a conventional standard cell library 102 for use in a place-and-route layout creation. In order to accommodate different driving capabilities, the conventional standard cell library 102 may include cells of different heights, such as a cell 110 has seven tracks, a cell 120 has nine tracks and a cell 130 has eleven tracks. Here the word, track, is used to describe the cell height. A track is typically referred to one contact pitch. A seven-track cell means that a transistor channel width in the cell is seven contact pitch wide. When these cells 110, 120 and 130 of different heights are used in place-and-route layout creation, a consideration of larger driving capability requires taller cells, while a consideration of low leakage and low power demands shorter cells. Mixing tall cells with shorter cells will sacrifice layout area utilization, as tall cells demand greater area for cell placement and/or tiling.
As such, what is desired is a place-and-route method that uses cells having the same height and thus having the same footprint for optimizing layout arrangement.